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Effective safety property checking using simulation-based sequential ATPGSHENG, Shuo; TAKAYAMA, Koichiro; HSIAO, Michael S et al.Design automation conference. 2002, pp 813-818, isbn 1-58113-461-4, 6 p.Conference Paper

Effective diagnostics through interval unloads in a BIST environmentWOHL, Peter; WAICUKAUSKI, John A; PATEL, Sanjay et al.Design automation conference. 2002, pp 249-254, isbn 1-58113-461-4, 6 p.Conference Paper

Signal integrity fault analysis using reduced-order modelingATTARHA, Amir; NOURANI, Mehrdad.Design automation conference. 2002, pp 367-370, isbn 1-58113-461-4, 4 p.Conference Paper

Theoretical properties of LFSRs for built-in self testDUFAZA, C.Integration (Amsterdam). 1998, Vol 25, Num 1, pp 17-35, issn 0167-9260Article

A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault DetectionKIM, Moonjoon; LEE, Jeongmin; HONG, Wongi et al.Lecture notes in computer science. 2006, pp 577-583, issn 0302-9743, isbn 3-540-34070-X, 7 p.Conference Paper

Functionality fault model : A basis for technology-specific test generationZEMVA, A; ZAJC, B.Microelectronics and reliability. 1998, Vol 38, Num 4, pp 597-604, issn 0026-2714Article

Pattern matching assisted modeling test pattern generationLE HONG; QIAO LI; JIAN RAO et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7274, issn 0277-786X, isbn 978-0-8194-7527-5 0-8194-7527-0, 727429.1-727429.0, 2Conference Paper

Test generation for technology-specific multi-faults based on detectable perturbationsZEMVA, Andrej; ZAJC, Baldomir.Microelectronics and reliability. 2005, Vol 45, Num 1, pp 163-173, issn 0026-2714, 11 p.Article

Efficient identification of crosstalk induced slowdown targetsBREUER, Melvin A; GUPTA, Sandeep K; NAZARIAN, Shahin et al.Asian test symposium. 2004, pp 124-131, isbn 0-7695-2235-1, 1Vol, 8 p.Conference Paper

A hybrid-type test pattern generating mechanismCHEN, Chuen-Yau; HSU, An-Chi.IEEE International Symposium on Circuits and Systems. 2004, pp 225-228, isbn 0-7803-8251-X, 4 p.Conference Paper

Approximate equivalence verification for protocol interface implementation via Genetic AlgorithmsCORNO, F; SONZA REORDA, M; SQUILLERO, G et al.Lecture notes in computer science. 1999, pp 182-192, issn 0302-9743, isbn 3-540-65837-8Conference Paper

Cellular automata for weighted random pattern generationNEEBEL, D. J; KIME, C. R.IEEE transactions on computers. 1997, Vol 46, Num 11, pp 1219-1229, issn 0018-9340Article

Conception et réalisation d'un planificateur de test hiérarchisé pour circuits logiques complexes = Conception and realization of a hierarchical test planner for complex logical circuitsGentil, Marie-Hélène; Durante, Christian.1994, 225 p.Thesis

Test vector generation and classification using FSM traversalsMARCZYNSKI, Ralph; THORNTON, Mitchell A; SZYGENDA, Stephen A et al.IEEE International Symposium on Circuits and Systems. 2004, pp 309-312, isbn 0-7803-8251-X, 4 p.Conference Paper

Weighted pseudo-random BIST for N-detection of single stuck-at faultsCHAOWEN YU; REDDY, Sudhakar M; POMERANZ, Irith et al.Asian test symposium. 2004, pp 178-183, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper

Verifying properties using sequential ATPGABRAHAM, Jacob A; VEDULA, Vivekananda M; SAAB, Daniel G et al.Proceedings - International Test Conference. 2002, pp 194-202, issn 1089-3539, isbn 0-7803-7542-4, 9 p.Conference Paper

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring countersCHAKRABARTY, Krishnendu; MURRAY, Brian T; IYENGAR, Vikram et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 633-636, issn 1063-8210Conference Paper

Minimizing power consumption in scan testing : Pattern generation and DFT techniquesBUTLER, Kenneth M; SAXENA, Jayashree; FRYARS, Tony et al.International Test Conference. 2004, pp 355-364, isbn 0-7803-8580-2, 1Vol, 10 p.Conference Paper

Computer-aided test flow in core-based designZIVKOVIC, V. A; TANGELDER, R. J. W. T; KERKHOFF, H. G et al.Microelectronics journal. 2000, Vol 31, Num 11-12, pp 999-1008, issn 0959-8324Conference Paper

Logic testing of bridging faults in CMOS integrated circuitsCHESS, B; LARRABEE, T.IEEE transactions on computers. 1998, Vol 47, Num 3, pp 338-345, issn 0018-9340Article

An efficient test generation for multiple fault coverage of two-rail checkersPANG, J. C. W; WONG, M. W. T; LEE, Y. S et al.International journal of electronics. 1997, Vol 83, Num 6, pp 837-848, issn 0020-7217Article

Nonscan design-for-testability techniques using RT-level design informationDEY, S; POTKONJAK, M.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 12, pp 1488-1506, issn 0278-0070Article

Program slicing for ATPG-based property checkingVEDULA, Vivekananda M; TOWNSEND, Whitney J; ABRAHAM, Jacob A et al.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 591-596, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

Test power reduction with multiple capture ordersLEE, Kuen-Jong; HSU, Shaing-Jer; HO, Chia-Ming et al.Asian test symposium. 2004, pp 26-31, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper

VirtualScan : A new compressed scan technology for test cost reductionWANG, Laung-Terng; XIAOQING WEN; FURUKAWA, Hiroshi et al.International Test Conference. 2004, pp 916-925, isbn 0-7803-8580-2, 1Vol, 10 p.Conference Paper

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